1. Field of the Invention
The present invention relates to a phase detector and particularly to a phase detector having a half-transparent module with an output-latched characteristic.
2. The Prior Arts
Phase detector is an important building block of many de-skewing circuits, such as the delay-locked loop (abbreviated as DLL), the phase locked loop (PLL) and the clock/data recovery circuit. The smallest detectable phase difference of the phase detector has a linear relationship with the phase resolution of de-skewing circuits. The smaller the detectable phase difference of the phase detector (or the smaller the dead zone) is, the higher the phase resolution. Moreover, the operating speed of the phase detector can affect the maximum operating frequency of the de-skewing circuits. In these regards, the most important design requirements of the phase detector are high speed and high resolution.
Referring to FIG. 1a and FIG. 1b, a high speed and high resolution phase detector in the prior art and the circuit of a half-transparent (HT) module of the phase detector are depicted, respectively. As shown in FIG. 1a, the phase detector 1 receives input signals CK_ref and CK_fb. The half-transparent module 12 is formed with two cascaded logic operation units 10, 11 as shown in FIG. 1b. The logic operation unit 10 is formed with two PMOS transistors M0 and M1 and one NMOS transistor M2. Both MOS transistors M0 and M2 receive a first input signal y, and the MOS transistor M1 receives a second input signal x.
The logic operation unit 11 is formed with one PMOS transistor M3 and two cascaded NMOS transistors M4 and M5. Both MOS transistors M3 and M5 receive an output signal w from the logic operation unit 10, and the MOS transistor M4 receives the control signal x. The output of the logic operation unit 11 is also the output signal ˜z of the half-transparent module 12.
Referring to FIG. 1c, two sets of timing, Timing 1 and Timing 2, of the half-transparent module shown in FIG. 1b are shown, respectively. In timing 1, a rising edge of the first input signal y has a phase lag with respect to that of the second input signal x. In Timing 2, a rising edge of the first input signal y has a phase lead with respect to that of the second input signal x. Taking the operation of Timing 1 as an example, when the first and second input signals y, x are both low (i.e. y=0 and x=0), the transistors M0 and M1 are both turned on. At this time, the output signal w of the logic operation unit 10 rises to high, turning off PMOS transistor M3 and turning on NMOS transistor M5. At this time, since the second input signal x is low, NMOS transistor M4 in the logic operation unit 11 is also turned off, keeping the output signal ˜z of the half-transparent module 12 at the previous state thereof (e.g. high state).
When the second input signal x begins to transit to high, transistor M1 of the logic operation unit 10 is turned off, and transistor M4 of the logic operation unit 11 is turned on to pull down the output signal ˜z of the half-transparent module 12. The output signal ˜z keeps stay low until the first input signal y transits to high. This is because that the output signal w of the logic operation unit 10 will transit to low as the first input signal y becomes high, turning on the PMOS transistor M3 and thus turning off the NMOS transistor M5 of the second logic operation unit 11. At this time, the output signal ˜z of the half-transparent module 12 is pulled high.
In summary, when the rising edge of the first input signal y has a phase lag with respect to the second input signal x, the output signal ˜z has the time when it stays low being equal to a phase difference of the first and second input signals y and x.
Similarly, we can deduce from Timing 2 that if the rising edge of the first input signal y leads that of the second input signal x, the output signal ˜z of the half-transparent module 12 maintains high owing to absence of a discharging path.
In conclusion, when the condition is met where the first input signal y has its rising edge lagging that of the second input signal x, the half-transparent module 12 will output a low pulse output having a pulse width equal to the phase difference of the two input signals x and y.
To detect the phase relationship of the input signals x and y, two identical half-transparent modules 12 of this kind are required to form the phase detector 1, shown in FIG. 1a, where input signals y and x for the upper and lower ones of the two identical half-transparent modules 12 are inversely connected.
From the above explanation, we know that the pulse width of the output signal ˜z becomes shorter as the rising edges of the two input signals y and x get closer to each other (i.e. the phase difference is smaller). To guarantee that the narrow pulse of the half-transparent module 12 can properly drive the subsequent circuit, it is required that the loading of the half-transparent module 12 is not too large; otherwise, the narrow pulse will be filtered out, making the subsequent circuit work improperly. Accordingly, this kind of phase detector 1 is generally applied to a charge pump-based loop configuration in which the phase detector only need to drive the charge pump. However, a phase detector used in a digital control loop has to drive a counter or a shift register composed of several flip-flops resulting in heavy loading. Thus, from the requirement of a small phase error, it is not appropriate to apply the above described phase detector 1 in the digital control loop.
To solve this problem, there was a flip-flop based phase detector suggested as a solution to the application of a digital control loop.
FIG. 2a is the diagram of the flip-flop based phase detector in the prior art. The flip-flop based phase detector 2 is composed of three buffers 20, 21, 22, two D-type flip-flops 23, 24, and two NOR gates 25, 26. Each of the flip-flops 23, 24 has a clock input terminal connected to the buffer 21 having a delay of d0 and connected to the buffer 22 having a delay of d1, respectively. The amount of the two delays are set different (d1>d0) to allow the flip-flops 23, 24 to grasp the same input signal A, which is the output of the buffer 20, at different points of time. The output signals D, E and F of flip-flops 23, 24 are operated with the NOR gates 25, 26 to generate output signals UP/˜DOWN and LOCK of the flip-flop based phase detector 2 to determine the phase relationship, i.e., phase lag, phase lead, or phase lock, between the two input signals CK_ref and CK_fb.
FIG. 2b is the plot of three sets of timing, Timing 1, Timing 2 and Timing 3, occurring on the flip-flop based phase detector 2 shown in FIG. 2a. Refer to Timing 1 in FIG. 2b, if the values of signal A at two time points when signal B and signal C rise are high, it can be judged that the input signal CK_ref has a phase lead with respect to the input signal CK_fb. In this case, after detecting the phase relationship, the output signal UP/˜DOWN transits to low and the output signal LOCK maintains at low level. Refer to Timing 2 in FIG. 2b, if the values of signal A at two time points when signal B and signal C rise are low, it can be judged that the input signal CK_ref has a phase lag with respect to the input signal CK_fb. In this case, the output signal UP/˜DOWN maintains at high level while the output signal LOCK maintains at low level. Refer to Timing 3 in FIG. 2b, if the signal A is low and high, respectively, when the signals B and C rise, it is judged that the input signals CK_ref and CK2_fb lock with each other. In this case, the output signal UP/˜DOWN transits to low level and the output signal LOCK transits to high level.
From above descriptions, we know that the two output signals UP/˜DOWN and LOCK are generated through the logic operation on the latched output signals of flip-flops 23 or 24. Therefore, UP/˜DOWN and LOCK are stable logic signals, but not pulsed signals. Accordingly, such kind of phase detector 2 can be used in a digital control loop.
The flip-flop based phase detector 2 has a dead zone approximately equal to the time difference between the signals B and C. In the prior art, the dead zone is designed as small as 160 ps. To reduce the dead zone, the buffer 22 generating the signal C should be sized up to shorten the time d1. However, the up sized buffer 22 will increase the loading of the clock signal CK_fb. Therefore, such a design not only induces higher power consumption but also enlarges the loading difference between the signals CK_ref and CK_fb.
Referring next to FIG. 3a, in which another flip-flop based phase detector in the prior art is depicted. This kind of phase detector 3 is composed of two buffers 30 and 31, three D-type flip-flops 32, 33, 34, XOR logic gates 35, 36 and an OR logic gate 37. In the phase detector 3, the buffer 30 has a delay d and is connected to a clock input terminal of the flip-flop 33, and the buffer 31 also has a delay d and is connected to a data input terminal of the flip-flop 34. The buffers 30 and 31 are used to provide a delay to the input signals CK_fb and CK_ref, respectively. The flip-flop 32 generates an output signal UP/˜DOWN. The flip-flops 33 and 34 generate output signals C and D, respectively, and these signals are subsequently sent to the XOR gates 35, 36 and OR gate 37 to generate another output signal LOCK. Similarly, the output signals UP/˜DOWN and LOCK are used to determine whether a phase lead, phase lag or phase lock exists between the input signals CK_ref and CK_fb.
FIG. 3b is a plot of three sets of timing, Timing 1, Timing 2 and Timing 3, of the flip-flop based phase detector shown in FIG. 3a, With respect to Timing 1, if both the signals CK_ref and B are high when the signal CK_fb rises and if the signal CK_ref is high when the signal A rises, it can be judged that the input signal CK_ref has a phase lead with respect to the input signal CK_fb. In this case, the output signal UP/˜DOWN transits to high while the output signal LOCK transits to high for a duration of d and then transits to low again. Similarly, if both the signals CK_ref and B are low when the signal CK_fb rises and the signal CK_ref is low when the signal A rises, it can be judged that the input signal CK_ref has a phase lag with respect to the input signal CK_fb. In this case, both the output signals UP/˜DOWN and LOCK are maintained at low level. In the other respect, if the signal CK_ref is high and the signal B is low when the signal CK_fb rises and if the signal CK_ref is high when the signal A rises, it can be judged that the input signals CK_ref and CK_fb lock with each other. In this case, both the output signals UP/˜DOWN and LOCK transit to high level.
It can be seen that the two output signals UP/˜DOWN and LOCK of the flip-flop based phase detector 3 are generated from stable outputs provided by flip-flops 32, 33 or 34. Accordingly, such kind of phase detector 3 may be used in a digital control loop.
In this kind of phase detector 3, the dead zone is approximately equal to the delay time d provided by buffer 30. To reduce the dead zone, we can up size buffer 30 to reduce the delay d. However, the up sized buffer 30 will increase the loading of the clock signal CK_fb and the power consumption contributed by buffer 30 itself. Therefore, such a design not only induces higher power consumption but also enlarges the loading difference between the signals CK_ref and CK_fb.
FIG. 4 is yet another flip-flop based phase detector in the prior art. The phase detector 4 is composed of two buffers 40 and 41, three D-type flip-flops 42, 43 and 44, a three-input AND gate 47, two two-input AND gates 45, 46, and a two-input OR gate 48. The phase detector 4 receives two input signals CK_ref and CK_fb and generates two output signals UP and DOWN.
In this kind of phase detector 4, the dead zone is approximately equal to the delay time d of the input buffer 40. To reduce the dead zone, we can up size buffer 40. However, the up sized buffer 40 will increase the loading of the clock signal CK_ref and the power consumption contributed by buffer 40 itself. Therefore, such a design not only induces higher power consumption but also enlarges the loading difference between the signals CK_ref and CK_fb.
In summary, the flip-flop based phase detectors used in the prior art have the following disadvantages: (1) The dead zone is determined by the delay time of buffers. The delay time can not be reduced to a very small value. Large dead zones often induce high jitter for the control loop. (2) In case that the flip-flops have a too large setup time or a too large hold time, the dead zone is broadened further. (3) The two input clock signals are sampled by different flip-flops. If the characteristics of the flip-flops, say the setup time and the hold time, are different, the dead zones for phase lead and phase lag will be asymmetric. (4) The phase detector is so complicated that the circuit requires a larger chip area. (5) The phase detector is also complicated to induce high power consumption.
Referring next to FIG. 5, in which a dynamic circuit based phase detector in the prior art is depicted. The dynamic circuit based phase detector 5 is composed of two dynamic circuit modules 50 and 51 and two RS latches 52 and 53. Each RS latch is composed of two cross-coupled NOR gates. The dynamic circuit module 50 is composed of one PMOS transistor M0 and two NMOS transistors M1 and M2 connected in series. Both transistors M0 and M2 receive a precharge input signal CK_precharge, while transistor M1 receives an input signal CK_ref. The dynamic circuit module 51 is composed of one PMOS transistor M3 and two NMOS transistors M4 and M5 connected in series. The dynamic circuit module 51 has totally the same connection relationship with the dynamic circuit module 50, however with the transistor M4 connected to CK_fb. The RS latch 52 is provided to latch the output signals A and B of the dynamic circuit modules 50 and 51, and the RS latch 53 is provided to latch the output signals of the RS latch 52.
In this kind of phase detector 5, the dynamic circuit modules 50 and 51 are used to replace the flip-flops in the flip-flop-based phase detector and thus the complexity of the circuit is reduced. Furthermore, due to the inherent characteristic of high speed with the dynamic circuit, the dead zone is reduced. As a result, it has been proved that the phase detector 5 can be operated under the frequency of 1 GHz and have a dead zone smaller than 10 ps. However, the precharge signal CK_precharge is required to precharge the dynamic circuit modules 50 and 51 and the timing for CK_precharge should be carefully controlled. However, from the system point of view, it is difficult to generate a special precharge signal CK_precharge with a precise timing control. This effect retards the effectiveness of this kind of phase detector in the real applications.